[ImportVerilog] Functionality for real number format specifiers not defined

I initially added added some basic support for real number format specifiers in PR #8848 some months ago. Due to school I have been busy and unable to follow up. I believe the functionality still needs to be implemented. I apologize for forgetting about this until now. More info at **_IEEE 1800-2017 § 21.2.1.2 "Format specifications"_**.